This paper presents hardware implementation of an adaptive neural equalizer using Field Programmable Gate Array (FPGA). The adaptive neural equalizer is implemented using a Multi Layer Perceptions (MLP) neural network with the Back-Propagation (BP) algorithm. The network model has a three-layer structure which is comprised of an input layer, a hidden layer and an output layer. Then the MLP is implemented using FPGA. Computer simulation results show that the performance of the MLP equalizer using software and hardware implements are close to each other's. A single neuron was made using a schematic editor using FOUNDATION SEIRES program ver. (4.1i), and then it is used to build the complete adaptive neural equalizer. The software implementation utilization was 92% of the platform capacity on the FPGA.
4th Mosharaka International Conference on Communications, Signals and Coding (MIC-CSC 2011)
Congress
2011 Global Congress on Communications, Signals and Coding (GC-CSC 2011), 7-9 October 2011, Amman, Jordan
Pages
1-6
Topics
Digital Signal Processing Neural Networks
ISSN
2227-331X
DOI
BibTeX
@inproceedings{101CSC2011,
title={Implementation of Adaptive Neural Equalizer Using FPGA},
author={Thamer M. Jamel, and Sabah Obaidi, and Ban M. Al-Juboory},
booktitle={2011 Global Congress on Communications, Signals and Coding (GC-CSC 2011)},
year={2011},
pages={1-6},
doi={}},
organization={Mosharaka for Research and Studies}
}
