We describe a model of FPGA based systems realised with the Stochastic Activity Networks (SAN) formalism. The model can be used (i) to debug the FPGA circuit design synthesised from the high level description of the system, and (ii) to calculate the signal probabilities and transition densities of the FPGA circuit design, which are parameters that can be used for reliability analysis, power consumption estimation and pseudo random testing of digital circuit design. We validate the developed model by reproducing the results presented in other studies for some representative combinatorial circuits, and we explore the applicability of the proposed model in the analysis of real-world devices by analysing the actual implementation of a circuit for the generation of Cyclic Redundancy Check codes.
Track
DCS: Digital Communication Systems
Conference
4th International Conference on Communications, Networking and Information Technology (MIC-CNIT 2010), 3-5 December 2010, Amman, Jordan
Pages
28-33
Topics
Communication System Simulation Signal Processing for Communications
