An FPGA hardware evaluation for the final round SHA-3 candidate algorithms of the competition held by National Institute of Standards and Technology (NIST) in order to replace the old SHA1 and SHA2 with the new SHA3 for the purpose of ensuring a long term robustness of hash functions will be presented in this paper. The main goal of providing the hardware evaluation for these algorithms is to find the best algorithm among the selected finalist algorithms that will satisfy the new hashing algorithm standards. This is based on a comparison between each of the finalists in terms of security level, throughput, clock frequancey, area, and the cost. We expect that the results of the comparisons will lighten the way for choosing the next hashing algorithm (SHA-3) that will be the best in finding a short message digest from a variable length message, which will support the security requirements of applications in today ubiquitous and pervasive information infrastructure.
5th Mosharaka International Conference on Communications, Networking and Information Technology (MIC-CNIT 2011)
Congress
2011 Global Congress on Communications, Networking and Information Technology (GC-CNIT 2011), 16-18 December 2011, Dubai, UAE
Pages
33-38
Topics
Cryptography and Data Security Digital Signal Processing
ISSN
2227-331X
DOI
BibTeX
@inproceedings{234CNIT2011,
title={FPGA Performance Evaluation of SHA-3 Candidate Algorithms},
author={Yaser Jararweh, and Hala Tawalbeh, and Lo'ai Tawalbeh, and Abidalrahman Moh'd},
booktitle={2011 Global Congress on Communications, Networking and Information Technology (GC-CNIT 2011)},
year={2011},
pages={33-38},
doi={}},
organization={Mosharaka for Research and Studies}
}
