With the current demand for increased capacity and complexity in integrated circuits, it is imperative to find new ways that restrict design space without sacrificing optimality. The traditional microprocessor architecture has done this in an effective way by providing a general pattern to organize computation in hardware. However, there is a need to have efficient routing algorithms developed for the Network-on-Chip (NoC) communication infrastructure that will synchronize and communicate with other resources in a transparent manner. The key objective of this paper is to survey various network-on-chip (NoC) routing algorithms for tilebased multiprocessor templates and present a new routing strategy called Quad2.
2nd Mosharaka International Conference on Communications, Propagation, and Electronics (MIC-CPE 2009)
Congress
2009 Global Congress on Communications, Propagation, and Electronics (GC-CPE 2009), 6-8 February 2009, Amman, Jordan
Pages
--1
Topics
ISSN
2227-331X
DOI
BibTeX
@inproceedings{879CPE2009,
title={Routing algorithms for network-on-chip in tile-based multiprocessor templates},
author={Adnan K. Shaout, and Maia Johnson, and Shang-Yeu Chang, and Gheith A. Abandah},
booktitle={2009 Global Congress on Communications, Propagation, and Electronics (GC-CPE 2009)},
year={2009},
pages={--1},
doi={}},
organization={Mosharaka for Research and Studies}
}
