Mosharaka for Research and Studies
Login/Sign Up
Main Menu
Papers Menu
Quick Links
Next Congress

All Forthcoming Congresses


All Forthcoming Conferences

Update on Tuesday, 9 April 2024: Prof. Saher Albatran becomes Track Chairperson of APE@MIC-Power 2024.
Papers Links
  • Browse
  • Subjects
  • Years
  • CNIT
  • GC-CNIT 2010
  • 18.Cnf-39
Papers Published at GC-CNIT 2010
All 7 Papers
IDAuthors and TitlePages
18.Cnf-10 Mr. Muamer Mohammed
Dr. Norrozila Sulaiman
Mr. Osama A. Muhsin
A novel intrusion detection system by using intelligent data mining in WEKA environment
18.Cnf-15 Prof. Khireddine Abdelkrim
Mr. Djamel Derardja
Mr. J. Salvestrini
Artificial intelligence applied for a telecommunication satellite
18.Cnf-22 Mr. Jiri Libich
Prof. Stanislav Zvanovec
Thermal Influences of Buildings on Availability of Free Space Optical Links
18.Cnf-24 Mr. Saifur R. Sabuj
Mr. Md S. Islam
Suppression of intercarrier interference using self-cancellation data conjugate scheme in MIMO-OFDM system
18.Cnf-25 Mr. Saifur R. Sabuj
Mr. Zulfiker Mahmud
Mr. M. E. Mollah
Suppression ICI Self-Cancellation Technique in OFDM using ADS
18.Cnf-26 Mr. Majid Naghmash
Prof. Mohd F. Ain
Mr. Yin H. Chye
Low-power decimation filter design for SDR receiver applications

GS Citations

Dr. Cinzia Bernardeschi
Dr. Luca Cassano
Dr. Andrea Domenici
Dr. Paolo Masci
Analysis of FPGAs Using the SAN formalism
18.Cnf-39 Paper View Page
Title Analysis of FPGAs Using the SAN formalism
Authors Dr. Cinzia Bernardeschi, University of Pisa, Pisa, Italy
Dr. Luca Cassano, University of Pisa, Pisa, Italy
Dr. Andrea Domenici, University of Pisa, Pisa, Italy
Dr. Paolo Masci, University of Pisa, Pisa, Italy
Abstract We describe a model of FPGA based systems realised with the Stochastic Activity Networks (SAN) formalism. The model can be used (i) to debug the FPGA circuit design synthesised from the high level description of the system, and (ii) to calculate the signal probabilities and transition densities of the FPGA circuit design, which are parameters that can be used for reliability analysis, power consumption estimation and pseudo random testing of digital circuit design. We validate the developed model by reproducing the results presented in other studies for some representative combinatorial circuits, and we explore the applicability of the proposed model in the analysis of real-world devices by analysing the actual implementation of a circuit for the generation of Cyclic Redundancy Check codes.
Track DCS: Digital Communication Systems
Conference 4th Mosharaka International Conference on Communications, Networking and Information Technology (MIC-CNIT 2010)
Congress 2010 Global Congress on Communications, Networking and Information Technology (GC-CNIT 2010), 3-5 December 2010, Amman, Jordan
Pages 28-33
Topics Communication System Simulation
Signal Processing for Communications
ISSN 2227-331X
BibTeX @inproceedings{39CNIT2010,
title={Analysis of FPGAs Using the SAN formalism},
author={Cinzia Bernardeschi, and Luca Cassano, and Andrea Domenici, and Paolo Masci},
booktitle={2010 Global Congress on Communications, Networking and Information Technology (GC-CNIT 2010)},
organization={Mosharaka for Research and Studies} }
Paper Views 73 Paper Views Rank 111/524
Paper Downloads 27 Paper Downloads Rank 225/524
GC-CNIT 2010 Visits: 17316||MIC-CNIT 2010 Visits: 14551||DCS Track Visits: 5958