This paper presents the comparison of DSP and FPGA based implementation of space code correlator (SCC) beamformer which is practical to use in cdma2000 systems. Implementation methodology is demonstrated and results regarding beamforming accuracy, weight vector computation time (execution time), and resource utilization are presented. The SCC algorithm is implemented on different Texas Instruments (TI) TMS320C6713 floating-point digital signal processors (DSP) and Xilinx’s VirtexIV family FPGA. The cdma2000 reverse link signal model is used and tested for uniform linear under varying multipath propagation conditions. The results show that DSP based SCC beamformer can estimate weight vectors within less than 10 ms with DOA search resolution of Δ=2° especially when C6713 DSP is used and it can be achieved within less than 25 μs on Virtex IV FPGA.
2nd Mosharaka International Conference on Communications, Propagation, and Electronics (MIC-CPE 2009)
Congress
2009 Global Congress on Communications, Propagation, and Electronics (GC-CPE 2009), 6-8 February 2009, Amman, Jordan
Pages
--1
Topics
FPGA Design and Implementation Software-Defined Radio
ISSN
2227-331X
DOI
BibTeX
@inproceedings{573CPE2009,
title={Comparison of Space Code Correlator Beamformer Using DSP and FPGA Implementations},
author={Sener Dikmese, and Adnan Kavak, and Kerem Kucuk, and , and Ali Tangel, and },
booktitle={2009 Global Congress on Communications, Propagation, and Electronics (GC-CPE 2009)},
year={2009},
pages={--1},
doi={}},
organization={Mosharaka for Research and Studies}
}
