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Update on Tuesday, 10 August 2021: Paper 1.Cnf-139@MIC-MCWC 2006 reaches 645 views and 244 downloads.
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  • GC-ElecEng 2020
  • 29.Cnf-1157
ElecEng Congresses with Published Papers
GC-ElecEng 2020, Valencia
GC-ElecEng 2021, Valencia
Papers Published at GC-ElecEng 2020
All 9 Papers
IDAuthors and TitlePages
29.Cnf-105 Dr. Alex Vukovic
Ms. Ayat Alrjoub
Furthering Innovation in Hyper Communication Era
29.Cnf-113 Prof. Càndid Reig
Dr. Maria-Dolores Cubells-Beltran
Mr. Javio Sanchis-Muñoz
Prof. Fernando Pardo
Dr. Jose A. Boluda
Dr. Francisco Vegara
Dr. Susana Cardoso
Address Event Representation (AER) approach to resistive sensor arrays

GS Citations

Prof. Cebrail Ciflikli
Mr. Kadir Aba
Implementing low cost and secure data transmission layer for image transmission in wireless sensor network
29.Cnf-221 Mrs. Aicha Mchbal
Dr. Naima Amar Touhami
Dr. El Ftouh Hanae
Dr. Aziz Dkiouak
Four-element UWB MIMO Antenna Design
29.Cnf-313 Dr. Joan Bas
Dr. Alexis Dowhuszko
Linear Time-Packing Detectors for Optical Feeder Link in High Throughput Satellite Systems
29.Cnf-1144 Mrs. Fériel Boulfani
Dr. Xavier Gendre
Prof. Anne Ruiz-Gazen
Mrs. Martina Salvignol
Anomaly detection for aircraft electrical generator using machine learning in a functional data framework
29.Cnf-1145 Mr. Nabil Morri
Dr. Sameh Hadouaj
Mr. Lamjed Ben Said
Towards an Intelligent control system for public transport traffic efficiency KPIs optimization
29.Cnf-1146 Mr. Ismail Moufid
Prof. Hassane El Markhi
Hassan El Moussaoui
Lamhamdi Tijani
Distribution network reconfiguration for power loss minimization using soft open point

GS Citations

Dr. Shaobo Chen
Dr. Hongwei Liu
UWB slot antenna on shielding can for high accuracy positioning application
29.Cnf-1157 Paper View Page
Title Performance Optimization of Semi-Custom Memory in 7nm FPGA
Authors Mr. Sourabh Aditya Swarnkar, Xilinx India, Hyderabad, India
Mr. Mohammad Anees, Xilinx India, Hyderabad, India
Mr. Kumar Rahul, Xilinx India, Hyderabad, India
Mr. Santosh Yachareni, Xilinx India, Hyderabad, India
Abstract Designing memories which embeds multiple features involves greater challenges. Adding additional features to memory degrades memory performance. Application demanding more features and high-performance memory, creates design challenges. Designing a feature rich memory using complete custom approach make the design turnaround time more. So, the memory implementation follows a hybrid of custom and digital design. Defining the optimal clock-distribution network in such feature rich designs is one of the most important aspect of high-speed SoC design. This paper demonstrates the custom approach by prioritizing the various features in terms of criticality of the timing requirements and significantly improve the clock tree performance. This approach opens new possibility for designing feature rich memory with high chances of first pass design on silicon. These kinds of memories can be seen in the FPGA’s, CPU’s, GPU’s.
Track Electronics: Electronic Engineering and Applications
Conference 1st Mosharaka International Conference on Emerging Applications of Electrical Engineering (MIC-ElectricApps 2020)
Congress 2020 Global Congress on Electrical Engineering (GC-ElecEng 2020), 4-6 September 2020, Valencia, Spain
Pages --1
Topics Timing and Clocking Circuits
System and Circuit Synthesis
ISSN 2227-331X
BibTeX @inproceedings{1157ElecEng2020,
title={Performance Optimization of Semi-Custom Memory in 7nm FPGA },
author={Sourabh Aditya Swarnkar, and Mohammad Anees, and Kumar Rahul, and Santosh Yachareni},
booktitle={2020 Global Congress on Electrical Engineering (GC-ElecEng 2020)},
organization={Mosharaka for Research and Studies} }
Paper Views 67 Paper Views Rank 147/524
Paper Downloads 27 Paper Downloads Rank 225/524
GC-ElecEng 2020 Visits: 34534||MIC-ElectricApps 2020 Visits: 24122||Electronics Track Visits: 3908