Designing memories which embeds multiple features involves greater challenges. Adding additional features to memory degrades memory performance. Application demanding more features and high-performance memory, creates design challenges. Designing a feature rich memory using complete custom approach make the design turnaround time more. So, the memory implementation follows a hybrid of custom and digital design. Defining the optimal clock-distribution network in such feature rich designs is one of the most important aspect of high-speed SoC design. This paper demonstrates the custom approach by prioritizing the various features in terms of criticality of the timing requirements and significantly improve the clock tree performance. This approach opens new possibility for designing feature rich memory with high chances of first pass design on silicon. These kinds of memories can be seen in the FPGA’s, CPU’s, GPU’s.
Track
Electronics: Electronic Engineering and Applications
Conference
1st Mosharaka International Conference on Emerging Applications of Electrical Engineering (MIC-ElectricApps 2020)
Congress
2020 Global Congress on Electrical Engineering (GC-ElecEng 2020), 4-6 September 2020 (Remotely), Valencia, Spain
Pages
--1
Topics
Timing and Clocking Circuits System and Circuit Synthesis
ISSN
2227-331X
DOI
BibTeX
@inproceedings{1157ElecEng2020,
title={Performance Optimization of Semi-Custom Memory in 7nm FPGA },
author={Sourabh Aditya Swarnkar, and Mohammad Anees, and Kumar Rahul, and Santosh Yachareni},
booktitle={2020 Global Congress on Electrical Engineering (GC-ElecEng 2020)},
year={2020},
pages={--1},
doi={}},
organization={Mosharaka for Research and Studies}
}
